The key to good ESD tolerant designs is to understand the basic causes, the various solutions to different requirements, and a good first order analysis of possible paths of the ESD energy for non-standard designs. Although the implementation approach may change for each new technology, the fundamentals remain the same for all technologies:
  1. Identify all current paths from the test pin to "any other pin" or any other supply pin other than the pin being tested.
  2. All designs must have robust performance to both positive and negative ESD pulses. Therefore, good substrate clamp diodes must be employed.
  3. The best ESD solutions utilize symmetrical / balanced current paths for the ESD energy. Therefore, it is very important on how the I/O pads are laid out.
  4. Also, the best ESD solutions utilize a combination of primary and secondary protection.
  5. Deep sub-micron technologies utilize shunt devices as well as NMOS breakdown (snap-back) devices because SCR protection is less effective than in the older 0.5 and 0.6 micron technologies.

As design experience increases and new I/O's are developed in the new technologies, it is necessary to test all I/O's to failure. Also, failure analysis must be performed on all failures and the results fed back to the design community so that new and improved methods can be implemented on future designs.