This discussion is intended to be a technical layman's description of the evolution and impact of salicided processes being used in current CMOS submicron technology. Some of the terminology may not be exactly correct as implemented by the process people in the various foundries or wafer fabrication centers (wafer fab). As can be seen from the table above, all transistor dimensions have shrunk by more than a factor of five (5) in both the linear (x, y) as well as the vertical dimensions as technology has moved from the 1.0 micron era to the current production technologies. This size reduction has resulted in an area reduction of more than 25X for the same function at higher speeds and dramatically lowers power. In addition, the number of interconnect layers has gone from one layer of poly and one layer of metal to as many as 4 layers of poly and 14 layers of metal. As the number of interconnect layers has increased, the thickness of the conductors has reduced causing increased current density leading to electomigration.

The earliest CMOS processes were made as simple as possible (20 to 40 process steps) to optimize yields and minimize silicon cost. As the CMOS processes matured, additional process steps could be added without significant cost (manufacturing complexity, yield, etc.) impact. The first "extra" process steps where separate N- and P- implants to adjust NMOS and PMOS threshold voltages (Vt). Later separate implants for both NWELL and PWELL created the "TWIN WELL" process. Also, some foundries began offering a second layer of metal which significantly reduced die sizes by helping solve the interconnect problem in IC layout. In the same time frame, a second layer of poly was offered to create two different voltage transistors as well as poly-to-poly capacitors for analog design. Other foundries offered silicided poly in order to lower the poly resistance from 40 ohms per square (or greater) to less than 10 ohms per square (2 to 4 ohms per square). This lower resistance poly could then be used as another layer of interconnect without compromising device performance (speed). As technologies moved below 0.5 microns, second order and third order effects along with wiring interconnect became more dominant in device performance. Additional layers of interconnect and implementation of 3-D modeling became important to meet performance requirements.

Today, technologies of 0.18 microns and less are now referred to as "deep submicron" technologies. As 0.18-micron technologies (and below) began to emerge, the need for lower resistance diffusions became a new requirement. Although every foundry (wafer fab) has a slightly different process, the "generic" name for processes with reduced resistance for poly interconnect and diffusions has become known as "salicided processes". These type processes evaporate or deposit metal on the surface of the silicon and then form a metal-to-silicon "stack" by alloying the metal to the silicon at a very high temperature (approximately 600°C). This process creates a thin metal-silicon alloy on the surface leaving the normal silicon structure under this thin conductor. The normal silicon structure under the salicide layer is either N+ / P+ doped single-crystal silicon (drains, sources, guardrings, diodes, etc.) or N+ / P+ doped poly-crystalline silicon (poly gates or poly interconnect). These deep submicron technologies may have more than 200 process steps depending on the number of interconnect layers and different types of metals.

Although the salicided processes have the advantages of reduced resistance for high-speed performance, they also have the liability of degraded ESD performance. During the early introduction of salicided drains and sources, many people thought the salicided process was not compatible with good ESD performance due only to the basic process control related issues. However detailed failure analysis showed that the cause of failures was a "power distribution" problem. The non-salicided processes had a much higher drain-to-gate resistance that resulted in much better current "ballasting" for I/O geometries. The much lower diffusion resistance (1/10 or less) provided by the salicided processes eliminated this ballasting and during the ESD event localized heating caused excessive leakage or localized shorts. As a result, most "deep submicron" processes have now provided a masking option to reduce this problem. This mask allows removal or blockage of the metal in selected areas before the implementation of the actual high temperature salicide process. In regions without salicide, the sheet resistances become much higher (40 to 300 ohms per square versus 1 to 5 ohms per square when salicided). Careful design management of this resistance results in significantly improved ESD performance (2X to 4X improvement with examples of 500V ESD going to 2kV and 1kV going to 4kV) with little or no performance degradation. In fact, the modeling of I/O output drivers with higher gate resistance demonstrates reduced ground-bounce (noise) which is normally viewed as a performance improvement.

An additional variable which affects the ESD performance of an IC is the decision to use or not use an epitaxial process. This is generally referred to as an "EPI" or "non-EPI" process. An epitaxial process grows a very thin, lightly doped epitaxial layer on top of a highly doped (generally P+) layer. As these lightly doped layers have become thinner and thinner, it has become more difficult to control the resistivity of the lightly doped layer. Since this lightly doped layer directly affects the Vt of the devices, the control of the final doping of this layer is extremely important. As a result, a number of foundries have decided to utilize "non-EPI" processes for the deep submicron technologies.

The significance of this change is that with "EPI" processes, much of the ESD current can be shunted vertically through the thin epitaxial layer to the substrate. A P+ doped substrate is very low resistance and provides a low impedance path back to ground (Vss) or back to the most negative pin being used in a given ESD test. If a "non-EPI" process is used, then the vertical path to substrate is a relatively high impedance and as a result, all of the high ESD currents must be managed "horizontally". This is true for the design of all of the individual ESD components as well as the architectural strategy for the "chip level" ESD protection. With these "non-EPI" processes, all substrate current must be planned to be distributed through the metal interconnect and not through the substrate. Although current will be distributed through the substrate, it must be treated as a high impedance path under all considerations (even for by-pass capacitors). Quite often it is assumed that large by-pass capacitors provide a significant portion of the VDD to substrate protection and/or padring protection. However, if the metal and contact strategy to the substrate is not managed carefully for a "non-EPI" process, this protection will also be reduced. Implementation of "clamp diodes" is also very key to the design. All clamp diodes should be multi-fingered (long and narrow) with a maximum number of contacts and via's. Likewise the metal connections to these diodes should also be well planned.