Aragio Solutions has developed a library of System Interface and I/O cells for deep-submicron processes at various foundries (CSM, TSMC, UMC, etc). As a top design service provider of ESD protection, custom IO's, and mixed signal custom designs, Aragio offers a variety of cells. The system I/O and connectivity circuits l isted below are implemented in all of the key process nodes from 0.13 um and 90 nm with extensive work on-going in the 65 nm process node.

General-purpose I/Os
GPIO CSM, TSMC, UMC 0.13 um and 90 nm The wide portfolio of general purpose I/Os is targeted to meet the critical performance, power, area, and reliability (ESD and latch-up tolerance) requirements for IC designs. The general purpose I/O circuits include a full set of power pads, corner pad cells, breakers, and spacers. These designs are implemented with special design considerations for power supply sequencing requirements. A distributed Power-on-Control (POC) is used during power up and power down of the systems.
High performance IO Cells
LVDS Pad Set Full complement of LVDS cells necessary to create a padring. Includes LVDSin, LVDSout, LVDSIO, LVDSref, spacers, and power supply cells. The LVDSref is a precisions temperature compensated band-gap reference that is used to set the common mode voltage at 1.2 volt. The full set has been verified in silicon at multiple foundries and at multiple process nodes.
SSTL_18 Pad Set Full complement of SSTL cells necessary to create a padring to address the SSTL_18 (1.8 volts) requirements. Pad sets include low cost implementations with no on-die termination as well as DDR2 designs with on-die termination. Both the single-ended bi-directional IO cell and the differential clock cells are available. The pad set contains a single cell that can be used to control the drive strength of all of the drivers as well as spacers, power supply cells and a Vref cell to provide an external reference voltage to the single-ended receivers. The full set of cells have been verified in silicon at various foundries and at various process nodes.
SSTL_2 Pad Set Full complement of SSTL cells necessary to create a padring to address the SSTL_2 (2.5 volts) requirements. Pad sets include low cost implementations with no on-die termination and controlled slew-rate to minimize over-shoot and under-shoot. Both the single-ended bi-directional IO cell and the differential clock cells are available. The pad set contains spacers, power supply cells and a Vref cell to provide an external reference voltage to the single-ended receivers. The full set of cells have been verified in silicon at various foundries and at various process nodes.
USB 1.1 A Universal Serial Bus (USB 1.1 analog transceiver) bidirectional I/O Macro Cell with dedicated isolated power supplies.
Standard IO Interface with Special Requirements
Slew-Rate controlled CMOS Buffers A wide range of Slew-Rate-Controlled Schmitt-triggered bidirectional I/O cells with 2, 4, 8, 12, and 16-mA output drive capability. Depending on the applications, the slew-rate may be as low as 1-2 ns and as slow as 15 to 35 ns output slew for EMI sensitive applications. Options include standard CMOS receivers to receivers with selectable Schmitt triggers with 400-mV minimum input hysteresis.
Special CMOS Buffers Additional Schmitt-triggered bidirectional I/O cells are available with output drive extending to 24 mA with controlled output slew to minimize EMI / SSO issues as well as providing the capability for open-drain option (ODEN) for the driver, pull-up/pull-down options and other unique requirements.
Input only CMOS Receivers CMOS receivers with or without Schmitt-trigger input that are independent of the Power-on-Control (POC) feature with up to 200 MHz operation.
Analog timing functions
Oscillator Dedicated and programmable Oscillator cells that generate an asynchronous on-chip clock signal with an appropriate external oscillator crystal (1 MHz to 40 MHz). Options include the oscillator with power pads and full ESD protection integrated as a macro with the oscillator and options with the oscillator stand alone with the ASIC designer providing the required power pad cells.
PLL Phase-locked loop library cells designed to be embedded in a given ASIC as a standalone clock generation system. User designed digital control necessary for a wide range of applications. Frequency ranges of 100 MHz to greater than 1 GHz.

 

For more information about Aragio's I/O Cells,
contact sales@aragio.com or call 972.516.0999